Skip to content

[RFC][TableGen] Require DAG argument for complex operands in InstAlias #136411

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 2 commits into
base: main
Choose a base branch
from
+327 −316
Open

[RFC][TableGen] Require DAG argument for complex operands in InstAlias #136411

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
8d4c44b
[RFC][TableGen] Require DAG argument for complex operands in InstAlias
s-barannikov Mar 25, 2024
418dc94
Reuse existing variable; fix indentation
s-barannikov Apr 23, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
109 changes: 59 additions & 50 deletions llvm/lib/Target/AArch64/AArch64InstrFormats.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3028,8 +3028,12 @@ class BaseAddSubEReg64<bit isSub, bit setFlags, RegisterClass dstRegtype,

// Aliases for register+register add/subtract.
class AddSubRegAlias<string asm, Instruction inst, RegisterClass dstRegtype,
RegisterClass src1Regtype, RegisterClass src2Regtype,
int shiftExt>
RegisterClass src1Regtype, dag src2>
: InstAlias<asm#"\t$dst, $src1, $src2",
(inst dstRegtype:$dst, src1Regtype:$src1, src2)>;
class AddSubRegAlias64<string asm, Instruction inst, RegisterClass dstRegtype,
RegisterClass src1Regtype, RegisterClass src2Regtype,
int shiftExt>
: InstAlias<asm#"\t$dst, $src1, $src2",
(inst dstRegtype:$dst, src1Regtype:$src1, src2Regtype:$src2,
shiftExt)>;
Expand Down Expand Up @@ -3097,22 +3101,22 @@ multiclass AddSub<bit isSub, string mnemonic, string alias,

// Register/register aliases with no shift when SP is not used.
def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"),
GPR32, GPR32, GPR32, 0>;
GPR32, GPR32, (arith_shifted_reg32 GPR32:$src2, 0)>;
def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Xrs"),
GPR64, GPR64, GPR64, 0>;
GPR64, GPR64, (arith_shifted_reg64 GPR64:$src2, 0)>;

// Register/register aliases with no shift when either the destination or
// first source register is SP.
def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrx"),
GPR32sponly, GPR32sp, GPR32, 16>; // UXTW #0
GPR32sponly, GPR32sp,
(arith_extended_reg32_i32 GPR32:$src2, 16)>; // UXTW #0
def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrx"),
GPR32sp, GPR32sponly, GPR32, 16>; // UXTW #0
def : AddSubRegAlias<mnemonic,
!cast<Instruction>(NAME#"Xrx64"),
GPR64sponly, GPR64sp, GPR64, 24>; // UXTX #0
def : AddSubRegAlias<mnemonic,
!cast<Instruction>(NAME#"Xrx64"),
GPR64sp, GPR64sponly, GPR64, 24>; // UXTX #0
GPR32sp, GPR32sponly,
(arith_extended_reg32_i32 GPR32:$src2, 16)>; // UXTW #0
def : AddSubRegAlias64<mnemonic, !cast<Instruction>(NAME#"Xrx64"),
GPR64sponly, GPR64sp, GPR64, 24>; // UXTX #0
def : AddSubRegAlias64<mnemonic, !cast<Instruction>(NAME#"Xrx64"),
GPR64sp, GPR64sponly, GPR64, 24>; // UXTX #0
}

multiclass AddSubS<bit isSub, string mnemonic, SDNode OpNode, string cmp,
Expand Down Expand Up @@ -3176,15 +3180,19 @@ multiclass AddSubS<bit isSub, string mnemonic, SDNode OpNode, string cmp,
def : InstAlias<cmp#"\t$src, $imm", (!cast<Instruction>(NAME#"Xri")
XZR, GPR64sp:$src, addsub_shifted_imm64:$imm), 5>;
def : InstAlias<cmp#"\t$src1, $src2$sh", (!cast<Instruction>(NAME#"Wrx")
WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh), 4>;
WZR, GPR32sp:$src1,
(arith_extended_reg32_i32 GPR32:$src2, arith_extend:$sh)), 4>;
def : InstAlias<cmp#"\t$src1, $src2$sh", (!cast<Instruction>(NAME#"Xrx")
XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh), 4>;
XZR, GPR64sp:$src1,
(arith_extended_reg32_i64 GPR32:$src2, arith_extend:$sh)), 4>;
def : InstAlias<cmp#"\t$src1, $src2$sh", (!cast<Instruction>(NAME#"Xrx64")
XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh), 4>;
def : InstAlias<cmp#"\t$src1, $src2$sh", (!cast<Instruction>(NAME#"Wrs")
WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh), 4>;
WZR, GPR32:$src1,
(arith_shifted_reg32 GPR32:$src2, arith_shift32:$sh)), 4>;
def : InstAlias<cmp#"\t$src1, $src2$sh", (!cast<Instruction>(NAME#"Xrs")
XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh), 4>;
XZR, GPR64:$src1,
(arith_shifted_reg64 GPR64:$src2, arith_shift64:$sh)), 4>;

// Support negative immediates, e.g. cmp Rn, -imm -> cmn Rn, imm
def : InstSubst<cmpAlias#"\t$src, $imm", (!cast<Instruction>(NAME#"Wri")
Expand All @@ -3194,27 +3202,28 @@ multiclass AddSubS<bit isSub, string mnemonic, SDNode OpNode, string cmp,

// Compare shorthands
def : InstAlias<cmp#"\t$src1, $src2", (!cast<Instruction>(NAME#"Wrs")
WZR, GPR32:$src1, GPR32:$src2, 0), 5>;
WZR, GPR32:$src1, (arith_shifted_reg32 GPR32:$src2, 0)), 5>;
def : InstAlias<cmp#"\t$src1, $src2", (!cast<Instruction>(NAME#"Xrs")
XZR, GPR64:$src1, GPR64:$src2, 0), 5>;
XZR, GPR64:$src1, (arith_shifted_reg64 GPR64:$src2, 0)), 5>;
def : InstAlias<cmp#"\t$src1, $src2", (!cast<Instruction>(NAME#"Wrx")
WZR, GPR32sponly:$src1, GPR32:$src2, 16), 5>;
WZR, GPR32sponly:$src1,
(arith_extended_reg32_i32 GPR32:$src2, 16)), 5>;
def : InstAlias<cmp#"\t$src1, $src2", (!cast<Instruction>(NAME#"Xrx64")
XZR, GPR64sponly:$src1, GPR64:$src2, 24), 5>;

// Register/register aliases with no shift when SP is not used.
def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"),
GPR32, GPR32, GPR32, 0>;
GPR32, GPR32, (arith_shifted_reg32 GPR32:$src2, 0)>;
def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Xrs"),
GPR64, GPR64, GPR64, 0>;
GPR64, GPR64, (arith_shifted_reg64 GPR64:$src2, 0)>;

// Register/register aliases with no shift when the first source register
// is SP.
def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrx"),
GPR32, GPR32sponly, GPR32, 16>; // UXTW #0
def : AddSubRegAlias<mnemonic,
!cast<Instruction>(NAME#"Xrx64"),
GPR64, GPR64sponly, GPR64, 24>; // UXTX #0
GPR32, GPR32sponly,
(arith_extended_reg32_i32 GPR32:$src2, 16)>; // UXTW #0
def : AddSubRegAlias64<mnemonic, !cast<Instruction>(NAME#"Xrx64"),
GPR64, GPR64sponly, GPR64, 24>; // UXTX #0
}

class AddSubG<bit isSub, string asm_inst, SDPatternOperator OpNode>
Expand Down Expand Up @@ -3399,9 +3408,10 @@ class BaseLogicalSReg<bits<2> opc, bit N, RegisterClass regtype,
}

// Aliases for register+register logical instructions.
class LogicalRegAlias<string asm, Instruction inst, RegisterClass regtype>
class LogicalRegAlias<string asm, Instruction inst, RegisterClass regtype,
dag op2>
: InstAlias<asm#"\t$dst, $src1, $src2",
(inst regtype:$dst, regtype:$src1, regtype:$src2, 0)>;
(inst regtype:$dst, regtype:$src1, op2)>;

multiclass LogicalImm<bits<2> opc, string mnemonic, SDNode OpNode,
string Alias> {
Expand Down Expand Up @@ -3473,10 +3483,10 @@ multiclass LogicalReg<bits<2> opc, bit N, string mnemonic,
let Inst{31} = 1;
}

def : LogicalRegAlias<mnemonic,
!cast<Instruction>(NAME#"Wrs"), GPR32>;
def : LogicalRegAlias<mnemonic,
!cast<Instruction>(NAME#"Xrs"), GPR64>;
def : LogicalRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"),
GPR32, (logical_shifted_reg32 GPR32:$src2, 0)>;
def : LogicalRegAlias<mnemonic, !cast<Instruction>(NAME#"Xrs"),
GPR64, (logical_shifted_reg64 GPR64:$src2, 0)>;
}

// Split from LogicalReg to allow setting NZCV Defs
Expand All @@ -3496,10 +3506,10 @@ multiclass LogicalRegS<bits<2> opc, bit N, string mnemonic,
}
} // Defs = [NZCV]

def : LogicalRegAlias<mnemonic,
!cast<Instruction>(NAME#"Wrs"), GPR32>;
def : LogicalRegAlias<mnemonic,
!cast<Instruction>(NAME#"Xrs"), GPR64>;
def : LogicalRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"),
GPR32, (logical_shifted_reg32 GPR32:$src2, 0)>;
def : LogicalRegAlias<mnemonic, !cast<Instruction>(NAME#"Xrs"),
GPR64, (logical_shifted_reg64 GPR64:$src2, 0)>;
}

//---
Expand Down Expand Up @@ -3987,9 +3997,10 @@ class LoadStore8RO<bits<2> sz, bit V, bits<2> opc, string asm, dag ins,
let Inst{4-0} = Rt;
}

class ROInstAlias<string asm, DAGOperand regtype, Instruction INST>
class ROInstAlias<string asm, DAGOperand regtype, Instruction INST,
ro_extend ext>
: InstAlias<asm # "\t$Rt, [$Rn, $Rm]",
(INST regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0)>;
(INST regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ext 0, 0))>;

multiclass Load8RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
string asm, ValueType Ty, SDPatternOperator loadop> {
Expand All @@ -4015,7 +4026,7 @@ multiclass Load8RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
let Inst{13} = 0b1;
}

def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX"), ro_Xextend8>;
}

multiclass Store8RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
Expand All @@ -4040,7 +4051,7 @@ multiclass Store8RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
let Inst{13} = 0b1;
}

def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX"), ro_Xextend8>;
}

class LoadStore16RO<bits<2> sz, bit V, bits<2> opc, string asm, dag ins,
Expand Down Expand Up @@ -4087,7 +4098,7 @@ multiclass Load16RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
let Inst{13} = 0b1;
}

def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX"), ro_Xextend16>;
}

multiclass Store16RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
Expand All @@ -4112,7 +4123,7 @@ multiclass Store16RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
let Inst{13} = 0b1;
}

def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX"), ro_Xextend16>;
}

class LoadStore32RO<bits<2> sz, bit V, bits<2> opc, string asm, dag ins,
Expand Down Expand Up @@ -4159,7 +4170,7 @@ multiclass Load32RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
let Inst{13} = 0b1;
}

def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX"), ro_Xextend32>;
}

multiclass Store32RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
Expand All @@ -4184,7 +4195,7 @@ multiclass Store32RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
let Inst{13} = 0b1;
}

def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX"), ro_Xextend32>;
}

class LoadStore64RO<bits<2> sz, bit V, bits<2> opc, string asm, dag ins,
Expand Down Expand Up @@ -4231,7 +4242,7 @@ multiclass Load64RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
let Inst{13} = 0b1;
}

def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX"), ro_Xextend64>;
}

multiclass Store64RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
Expand All @@ -4256,7 +4267,7 @@ multiclass Store64RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
let Inst{13} = 0b1;
}

def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX"), ro_Xextend64>;
}

class LoadStore128RO<bits<2> sz, bit V, bits<2> opc, string asm, dag ins,
Expand Down Expand Up @@ -4303,7 +4314,7 @@ multiclass Load128RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
let Inst{13} = 0b1;
}

def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX"), ro_Xextend128>;
}

multiclass Store128RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
Expand All @@ -4324,7 +4335,7 @@ multiclass Store128RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
let Inst{13} = 0b1;
}

def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX"), ro_Xextend128>;
}

let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
Expand Down Expand Up @@ -4373,9 +4384,7 @@ multiclass PrefetchRO<bits<2> sz, bit V, bits<2> opc, string asm> {
let Inst{13} = 0b1;
}

def : InstAlias<"prfm $Rt, [$Rn, $Rm]",
(!cast<Instruction>(NAME # "roX") prfop:$Rt,
GPR64sp:$Rn, GPR64:$Rm, 0, 0)>;
def : ROInstAlias<"prfm", prfop, !cast<Instruction>(NAME # "roX"), ro_Xextend64>;
}

//---
Expand Down
78 changes: 54 additions & 24 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2416,13 +2416,17 @@ defm ADD : AddSub<0, "add", "sub", add>;
defm SUB : AddSub<1, "sub", "add">;

def : InstAlias<"mov $dst, $src",
(ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0)>;
(ADDWri GPR32sponly:$dst, GPR32sp:$src,
(addsub_shifted_imm32 0, 0))>;
def : InstAlias<"mov $dst, $src",
(ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0)>;
(ADDWri GPR32sp:$dst, GPR32sponly:$src,
(addsub_shifted_imm32 0, 0))>;
def : InstAlias<"mov $dst, $src",
(ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0)>;
(ADDXri GPR64sponly:$dst, GPR64sp:$src,
(addsub_shifted_imm64 0, 0))>;
def : InstAlias<"mov $dst, $src",
(ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0)>;
(ADDXri GPR64sp:$dst, GPR64sponly:$src,
(addsub_shifted_imm64 0, 0))>;

defm ADDS : AddSubS<0, "adds", AArch64add_flag, "cmn", "subs", "cmp">;
defm SUBS : AddSubS<1, "subs", AArch64sub_flag, "cmp", "adds", "cmn">;
Expand Down Expand Up @@ -2482,19 +2486,31 @@ def : Pat<(AArch64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
(ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
}

def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
def : InstAlias<"neg $dst, $src",
(SUBWrs GPR32:$dst, WZR,
(arith_shifted_reg32 GPR32:$src, 0)), 3>;
def : InstAlias<"neg $dst, $src",
(SUBXrs GPR64:$dst, XZR,
(arith_shifted_reg64 GPR64:$src, 0)), 3>;
def : InstAlias<"neg $dst, $src$shift",
(SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
(SUBWrs GPR32:$dst, WZR,
(arith_shifted_reg32 GPR32:$src, arith_shift32:$shift)), 2>;
def : InstAlias<"neg $dst, $src$shift",
(SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;

def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
(SUBXrs GPR64:$dst, XZR,
(arith_shifted_reg64 GPR64:$src, arith_shift64:$shift)), 2>;

def : InstAlias<"negs $dst, $src",
(SUBSWrs GPR32:$dst, WZR,
(arith_shifted_reg32 GPR32:$src, 0)), 3>;
def : InstAlias<"negs $dst, $src",
(SUBSXrs GPR64:$dst, XZR,
(arith_shifted_reg64 GPR64:$src, 0)), 3>;
def : InstAlias<"negs $dst, $src$shift",
(SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
(SUBSWrs GPR32:$dst, WZR,
(arith_shifted_reg32 GPR32:$src, arith_shift32:$shift)), 2>;
def : InstAlias<"negs $dst, $src$shift",
(SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
(SUBSXrs GPR64:$dst, XZR,
(arith_shifted_reg64 GPR64:$src, arith_shift64:$shift)), 2>;


// Unsigned/Signed divide
Expand Down Expand Up @@ -2921,31 +2937,45 @@ defm ORN : LogicalReg<0b01, 1, "orn",
BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
defm ORR : LogicalReg<0b01, 0, "orr", or>;

def : InstAlias<"mov $dst, $src", (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0), 2>;
def : InstAlias<"mov $dst, $src", (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0), 2>;

def : InstAlias<"mvn $Wd, $Wm", (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0), 3>;
def : InstAlias<"mvn $Xd, $Xm", (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0), 3>;
def : InstAlias<"mov $dst, $src",
(ORRWrs GPR32:$dst, WZR,
(logical_shifted_reg32 GPR32:$src, 0)), 2>;
def : InstAlias<"mov $dst, $src",
(ORRXrs GPR64:$dst, XZR,
(logical_shifted_reg64 GPR64:$src, 0)), 2>;

def : InstAlias<"mvn $Wd, $Wm",
(ORNWrs GPR32:$Wd, WZR,
(logical_shifted_reg32 GPR32:$Wm, 0)), 3>;
def : InstAlias<"mvn $Xd, $Xm",
(ORNXrs GPR64:$Xd, XZR,
(logical_shifted_reg64 GPR64:$Xm, 0)), 3>;

def : InstAlias<"mvn $Wd, $Wm$sh",
(ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh), 2>;
(ORNWrs GPR32:$Wd, WZR,
(logical_shifted_reg32 GPR32:$Wm, logical_shift32:$sh)), 2>;
def : InstAlias<"mvn $Xd, $Xm$sh",
(ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh), 2>;
(ORNXrs GPR64:$Xd, XZR,
(logical_shifted_reg64 GPR64:$Xm, logical_shift64:$sh)), 2>;

def : InstAlias<"tst $src1, $src2",
(ANDSWri WZR, GPR32:$src1, logical_imm32:$src2), 2>;
def : InstAlias<"tst $src1, $src2",
(ANDSXri XZR, GPR64:$src1, logical_imm64:$src2), 2>;

def : InstAlias<"tst $src1, $src2",
(ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0), 3>;
(ANDSWrs WZR, GPR32:$src1,
(logical_shifted_reg32 GPR32:$src2, 0)), 3>;
def : InstAlias<"tst $src1, $src2",
(ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0), 3>;
(ANDSXrs XZR, GPR64:$src1,
(logical_shifted_reg64 GPR64:$src2, 0)), 3>;

def : InstAlias<"tst $src1, $src2$sh",
(ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh), 2>;
(ANDSWrs WZR, GPR32:$src1,
(logical_shifted_reg32 GPR32:$src2, logical_shift32:$sh)), 2>;
def : InstAlias<"tst $src1, $src2$sh",
(ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh), 2>;
(ANDSXrs XZR, GPR64:$src1,
(logical_shifted_reg64 GPR64:$src2, logical_shift64:$sh)), 2>;


def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;
Expand Down
Loading
Loading