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[SelectionDAG] Take passthru into account when widening ISD::MLOAD #144170

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Merged
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Jun 14, 2025
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[SelectionDAG] Take passthru into account when widening ISD::MLOAD #144170

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mshockwave Jun 13, 2025
7cc1ea4
[SelectionDAG] Take passthru into account when widening ISD::MLOAD
mshockwave Jun 13, 2025
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17 changes: 15 additions & 2 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -6149,20 +6149,33 @@ SDValue DAGTypeLegalizer::WidenVecRes_MLOAD(MaskedLoadSDNode *N) {

if (ExtType == ISD::NON_EXTLOAD &&
TLI.isOperationLegalOrCustom(ISD::VP_LOAD, WidenVT) &&
TLI.isTypeLegal(WideMaskVT)) {
TLI.isTypeLegal(WideMaskVT) &&
// If there is a passthru, we shouldn't use vp.load. However,
// type legalizer will struggle on masked.load with
// scalable vectors, so for scalable vectors, we still use vp.load
// but manually merge the load result with the passthru using vp.select.
(N->getPassThru()->isUndef() || VT.isScalableVector())) {
Mask = DAG.getInsertSubvector(dl, DAG.getUNDEF(WideMaskVT), Mask, 0);
SDValue EVL = DAG.getElementCount(dl, TLI.getVPExplicitVectorLengthTy(),
VT.getVectorElementCount());
SDValue NewLoad =
DAG.getLoadVP(N->getAddressingMode(), ISD::NON_EXTLOAD, WidenVT, dl,
N->getChain(), N->getBasePtr(), N->getOffset(), Mask, EVL,
N->getMemoryVT(), N->getMemOperand());
SDValue NewVal = NewLoad;

// Manually merge with vp.select
if (!N->getPassThru()->isUndef()) {
assert(WidenVT.isScalableVector());
NewVal =
DAG.getNode(ISD::VP_SELECT, dl, WidenVT, Mask, NewVal, PassThru, EVL);
}

// Modified the chain - switch anything that used the old chain to use
// the new one.
ReplaceValueWith(SDValue(N, 1), NewLoad.getValue(1));

return NewLoad;
return NewVal;
}

// The mask should be widened as well
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13 changes: 13 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll
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Expand Up @@ -341,3 +341,16 @@ define <7 x i8> @masked_load_v7i8(ptr %a, <7 x i1> %mask) {
ret <7 x i8> %load
}

define <7 x i8> @masked_load_passthru_v7i8(ptr %a, <7 x i1> %mask) {
; CHECK-LABEL: masked_load_passthru_v7i8:
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 127
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.s.x v8, a1
; CHECK-NEXT: vmand.mm v0, v0, v8
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vle8.v v8, (a0), v0.t
; CHECK-NEXT: ret
%load = call <7 x i8> @llvm.masked.load.v7i8(ptr %a, i32 8, <7 x i1> %mask, <7 x i8> zeroinitializer)
ret <7 x i8> %load
}
22 changes: 21 additions & 1 deletion llvm/test/CodeGen/RISCV/rvv/masked-load-int.ll
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Expand Up @@ -21,7 +21,27 @@ define <vscale x 1 x i8> @masked_load_nxv1i8(ptr %a, <vscale x 1 x i1> %mask) no
%load = call <vscale x 1 x i8> @llvm.masked.load.nxv1i8(ptr %a, i32 1, <vscale x 1 x i1> %mask, <vscale x 1 x i8> undef)
ret <vscale x 1 x i8> %load
}
declare <vscale x 1 x i8> @llvm.masked.load.nxv1i8(ptr, i32, <vscale x 1 x i1>, <vscale x 1 x i8>)

define <vscale x 1 x i8> @masked_load_passthru_nxv1i8(ptr %a, <vscale x 1 x i1> %mask) nounwind {
; V-LABEL: masked_load_passthru_nxv1i8:
; V: # %bb.0:
; V-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
; V-NEXT: vmv.v.i v8, 0
; V-NEXT: vle8.v v8, (a0), v0.t
; V-NEXT: ret
;
; ZVE32-LABEL: masked_load_passthru_nxv1i8:
; ZVE32: # %bb.0:
; ZVE32-NEXT: csrr a1, vlenb
; ZVE32-NEXT: srli a1, a1, 3
; ZVE32-NEXT: vsetvli a2, zero, e8, mf4, ta, ma
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@mshockwave mshockwave Jun 13, 2025 •
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I think we should avoid this VL toggle... (vmv.v.i is an unmasked instruction anyway so the difference between ma/mu shouldn't matter)

; ZVE32-NEXT: vmv.v.i v8, 0
; ZVE32-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; ZVE32-NEXT: vle8.v v8, (a0), v0.t
; ZVE32-NEXT: ret
%load = call <vscale x 1 x i8> @llvm.masked.load.nxv1i8(ptr %a, i32 1, <vscale x 1 x i1> %mask, <vscale x 1 x i8> zeroinitializer)
ret <vscale x 1 x i8> %load
}

define <vscale x 1 x i16> @masked_load_nxv1i16(ptr %a, <vscale x 1 x i1> %mask) nounwind {
; V-LABEL: masked_load_nxv1i16:
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