Various adaptations needed for nrf92 IRONSide

boards/nordic/nrf9280pdk/Kconfig.defconfig

@@ -19,3 +19,13 @@ config ASSERT
 	default n if ZTEST
 
 endif # BOARD_NRF9280PDK_NRF9280_CPUPPR
+
+if BOARD_NRF9280PDK_NRF9280_CPUAPP_IRON
+
+config ROM_START_OFFSET
+	default 0x800 if BOOTLOADER_MCUBOOT
+
+config FLASH_LOAD_OFFSET
+	default 0x2c000 if !USE_DT_CODE_PARTITION
+
+endif # BOARD_NRF9280PDK_NRF9280_CPUAPP_IRON

boards/nordic/nrf9280pdk/Kconfig.nrf9280pdk

@@ -2,7 +2,9 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config BOARD_NRF9280PDK
-	select SOC_NRF9280_CPUAPP if BOARD_NRF9280PDK_NRF9280_CPUAPP
+	select SOC_NRF9280_CPUAPP if (BOARD_NRF9280PDK_NRF9280_CPUAPP || \
+					 BOARD_NRF9280PDK_NRF9280_CPUAPP_IRON)
 	select SOC_NRF9280_CPURAD if BOARD_NRF9280PDK_NRF9280_CPURAD
-	select SOC_NRF9280_CPUPPR if BOARD_NRF9280PDK_NRF9280_CPUPPR || \
-				     BOARD_NRF9280PDK_NRF9280_CPUPPR_XIP
+	select SOC_NRF9280_CPUPPR if (BOARD_NRF9280PDK_NRF9280_CPUPPR || \
+				     BOARD_NRF9280PDK_NRF9280_CPUPPR_XIP)
+	select SOC_NRF9280_IRON if BOARD_NRF9280PDK_NRF9280_CPUAPP_IRON

boards/nordic/nrf9280pdk/board.yml

@@ -7,3 +7,5 @@
     variants:
     - name: xip
       cpucluster: cpuppr
+    - name: iron
+      cpucluster: cpuapp

boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-ipc_conf_iron.dtsi

@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* This file is to be merged with the original ipc_conf.dtsi in the future. */
+
+/ {
+	ipc {
+		/delete-node/ ipc-1-2;
+		/delete-node/ ipc-1-3;
+
+		cpusec_cpuapp_ipc: ipc-1-2 {
+			compatible = "nordic,ironside-call";
+			memory-region = <&cpusec_cpuapp_ipc_shm>;
+			mboxes = <&cpusec_bellboard 12>,
+				 <&cpuapp_bellboard 0>;
+			status = "disabled";
+		};
+
+		cpusec_cpurad_ipc: ipc-1-3 {
+			compatible = "nordic,ironside-call";
+			memory-region = <&cpusec_cpurad_ipc_shm>;
+			mboxes = <&cpusec_bellboard 18>,
+				 <&cpurad_bellboard 0>;
+			status = "disabled";
+		};
+	};
+};

boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-memory_map.dtsi

@@ -197,8 +197,8 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-		cpuapp_slot0_partition: partition@442000 {
-			reg = <0x442000 DT_SIZE_K(1024)>;
+		cpuapp_slot0_partition: partition@33000 {
+			reg = <0x33000 DT_SIZE_K(1024)>;
 		};
 
 		cpuppr_code_partition: partition@542000 {

boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-memory_map_iron.dtsi

@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* This file is to be merged with the original memory_map.dtsi in the future.
+ * The following nodes will be replaced:
+ */
+/delete-node/ &cpuapp_cpusec_ipc_shm;
+/delete-node/ &cpuapp_cpusys_ipc_shm;
+/delete-node/ &cpurad_cpusec_ipc_shm;
+/delete-node/ &cpurad_cpusys_ipc_shm;
+/delete-node/ &cpusec_cpuapp_ipc_shm;
+/delete-node/ &cpusec_cpurad_ipc_shm;
+/delete-node/ &cpusys_cpuapp_ipc_shm;
+/delete-node/ &cpusys_cpurad_ipc_shm;
+/delete-node/ &cpuapp_rw_partitions;
+/delete-node/ &cpuapp_rx_partitions;
+/delete-node/ &cpurad_rx_partitions;
+
+/ {
+	reserved-memory {
+        cpuapp_cpusys_ipc_shm: memory@2f88fce0 {
+			reg = <0x2f88fce0 0x80>;
+		};
+
+		cpusys_cpuapp_ipc_shm: memory@2f88fd60 {
+			reg = <0x2f88fd60 0x80>;
+		};
+
+		cpurad_cpusys_ipc_shm: memory@2f88fe00 {
+			reg = <0x2f88fe00 0x80>;
+		};
+
+		cpusys_cpurad_ipc_shm: memory@2f88fe80 {
+			reg = <0x2f88fe80 0x80>;
+		};
+
+		cpusec_cpurad_ipc_shm: memory@2f88f800 {
+			reg = <0x2f88f800 0x80>;
+		};
+
+		cpurad_ironside_se_event_report: memory@2f88f880 {
+			reg = <0x2f88f880 0x100>;
+		};
+
+		cpurad_ironside_se_boot_report: memory@2f88f980 {
+			reg = <0x2f88f980 0x200>;
+		};
+
+		cpusec_cpuapp_ipc_shm: memory@2f88fb80 {
+			reg = <0x2f88fb80 0x80>;
+		};
+
+		cpuapp_ironside_se_event_report: memory@2f88fc00 {
+			reg = <0x2f88fc00 0x100>;
+		};
+
+		cpuapp_ironside_se_boot_report: memory@2f88fd00 {
+			reg = <0x2f88fd00 0x200>;
+		};
+	};
+};
+
+&mram1x {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		cpuapp_boot_partition: partition@2c000 {
+			reg = <0x2c000 DT_SIZE_K(64)>;
+		};
+
+		cpuapp_slot0_partition: partition@3c000 {
+			reg = <0x3c000 DT_SIZE_K(336)>;
+		};
+
+		cpurad_slot0_partition: partition@90000 {
+			reg = <0x90000 DT_SIZE_K(336)>;
+		};
+
+		cpuppr_code_partition: partition@e4000 {
+			reg = <0xe4000 DT_SIZE_K(64)>;
+		};
+
+		cpuflpr_code_partition: partition@f4000 {
+			reg = <0xf4000 DT_SIZE_K(48)>;
+		};
+
+		cpuapp_slot1_partition: partition@100000 {
+			reg = <0x100000 DT_SIZE_K(336)>;
+		};
+
+		cpurad_slot1_partition: partition@154000 {
+			reg = <0x154000 DT_SIZE_K(336)>;
+		};
+
+		storage_partition: partition@1a8000 {
+			reg = <0x1a8000 DT_SIZE_K(40)>;
+		};
+	};
+};

boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp_iron.dts

@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "nrf9280pdk_nrf9280_cpuapp.dts"
+#include "nrf9280pdk_nrf9280-ipc_conf_iron.dtsi"
+#include "nrf9280pdk_nrf9280-memory_map_iron.dtsi"
+
+/delete-node/ &cpusec_cpurad_ipc;
+
+/ {
+	chosen {
+		zephyr,code-partition = &slot0_partition;
+		zephyr,uart-mcumgr = &uart136;
+	};
+};
+
+&cpusec_bellboard {
+	status = "okay";
+};
+
+&cpusec_cpuapp_ipc {
+	mbox-names = "tx", "rx";
+	status = "okay";
+};
+
+boot_partition: &cpuapp_boot_partition {
+	label = "mcuboot";
+};
+
+slot0_partition: &cpuapp_slot0_partition {
+	label = "image-0";
+};
+
+slot1_partition: &cpuapp_slot1_partition {
+	label = "image-1";
+};

boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp_iron.yaml

@@ -0,0 +1,23 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: nrf9280pdk/nrf9280/cpuapp/iron
+name: nRF9280-DK-nRF9280-Application
+type: mcu
+arch: arm
+toolchain:
+  - gnuarmemb
+  - xtools
+  - zephyr
+sysbuild: true
+ram: 512
+flash: 1024
+supported:
+  - adc
+  - counter
+  - gpio
+  - i2c
+  - pwm
+  - spi
+  - watchdog
+  - usbd

boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp_iron_defconfig

@@ -0,0 +1,29 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable hardware stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# MPU-based null-pointer dereferencing detection cannot be applied
+# as the (0x0 - 0x400) region is unmapped for this target.
+CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
+
+# Enable cache
+CONFIG_CACHE_MANAGEMENT=y
+CONFIG_EXTERNAL_CACHE=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# UICR generation is not supported, and when reintroduced will not use nrf-regtool.
+CONFIG_NRF_REGTOOL_GENERATE_UICR=n

drivers/firmware/nrf_ironside/Kconfig

@@ -3,7 +3,7 @@
 
 config NRF_IRONSIDE
 	bool
-	depends on SOC_NRF54H20_IRON
+	depends on SOC_NRF54H20_IRON || SOC_NRF9280_IRON
 	help
 	  This is selected by drivers interacting with Nordic IRONside firmware.
 
@@ -28,11 +28,11 @@ config NRF_IRONSIDE_CALL_INIT_PRIORITY
 endif # NRF_IRONSIDE_CALL
 
 menu "Nordic IRONside services"
-	depends on SOC_NRF54H20_IRON
+	depends on SOC_NRF54H20_IRON || SOC_NRF9280_IRON
 
 config NRF_IRONSIDE_CPUCONF_SERVICE
 	bool "IRONside CPUCONF service"
-	depends on SOC_NRF54H20_CPUAPP
+	depends on SOC_NRF54H20_CPUAPP || SOC_NRF9280_CPUAPP
 	select NRF_IRONSIDE_CALL
 	help
 	  Service used to boot local domain cores.

samples/boards/nordic/nrf_ironside/update/sample.yaml

@@ -6,7 +6,10 @@
   tags: nrf_ironside
   integration_platforms:
     - nrf54h20dk/nrf54h20/cpuapp/iron
+    - nrf9280pdk/nrf9280/cpuapp/iron
 
 tests:
-  sample.boards.nordic.nrf_ironside.update:
-    platform_allow: nrf54h20dk/nrf54h20/cpuapp/iron
+  sample.drivers.firmware.nrf_ironside.update:
+    platform_allow: 
+    - nrf54h20dk/nrf54h20/cpuapp/iron
+    - nrf9280pdk/nrf9280/cpuapp/iron

soc/nordic/nrf92/CMakeLists.txt

@@ -10,3 +10,5 @@ zephyr_include_directories(.)
 # Ensure that image size aligns with 16 bytes so that MRAMC finalizes all writes
 # for the image correctly
 zephyr_linker_sources(SECTIONS SORT_KEY zzz_place_align_at_end align.ld)
+
+add_subdirectory(ironside/se)

soc/nordic/nrf92/Kconfig

@@ -7,6 +7,7 @@ config SOC_SERIES_NRF92X
 	select HAS_NRFS
 	select HAS_NRFX
 	select HAS_NORDIC_DRIVERS
+	select SOC_EARLY_INIT_HOOK if ARM
 	select NRF_PLATFORM_HALTIUM
 
 config SOC_NRF9230_ENGB_CPUAPP
@@ -48,3 +49,6 @@ config SOC_NRF9230_ENGB_CPURAD
 
 config SOC_NRF9230_ENGB_CPUPPR
 	select RISCV_CORE_NORDIC_VPR
+
+config SOC_NRF9280_IRON
+	select EXPERIMENTAL if MCUBOOT

soc/nordic/nrf92/Kconfig.soc

@@ -62,5 +62,10 @@ config SOC_NRF9280_CPUPPR
 	help
 	  nRF9280 CPUPPR
 
+config SOC_NRF9280_IRON
+	bool
+	help
+	  Indicates that local domain firmware is compatible with Nordic IRONside SE.
+
 config SOC
 	default "nrf9280" if SOC_NRF9280

soc/nordic/nrf92/ironside/se/CMakeLists.txt

@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Nordic Semiconductor
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library_sources_ifdef(CONFIG_SOC_NRF54H20_IRONSIDE_SE_BOOT_REPORT ironside_se_boot_report.c)
+zephyr_include_directories(include)

soc/nordic/nrf92/ironside/se/Kconfig

@@ -0,0 +1,15 @@
+# Copyright (c) 2025 Nordic Semiconductor
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_NRF9280_IRONSIDE_SE_BOOT_REPORT
+	bool "Nordic IRONside SE boot report"
+	default y if SOC_NRF9280_CPUAPP || SOC_NRF9251_CPUAPP
+	depends on SOC_NRF9280_IRON 
+	help
+	  This option enables parsing of the Boot Report populated by Nordic IRONside SE.
+
+config SOC_NRF9280_IRONSIDE_SE_BOOT_REPORT_MAGIC
+	hex
+	default 0x4d69546f
+	help
+	  Constant used to check if an Nordic IRONside SE boot report has been written.