Raise exception when RV32E instructions use x16-x31

[eleanorLYJ]

Modify rv_decode() to enforce RV32E register constraints by validating rd, rs1, rs2, and rs3, ensuring they remain within x0-x15. If an instruction attempts to use x16-x31, trigger an illegal instruction exception, aligning with RISC-V privileged architecture behavior.

According to The RISC-V Instruction Set Manual Volume I: Unprivileged Architecture, Version 20240411:

"RV32E and RV64E ... only registers x0-x15 are provided. All encodings specifying the other registers x16-x31 are reserved."

Summary by Bito

This pull request enhances the rv_decode() function by enforcing constraints on RV32E register usage, ensuring valid registers are limited to x0-x15. It improves instruction decoding robustness by triggering illegal instruction exceptions for invalid register usage. New variables and logic have been added for validation.

Unit tests added: False

Estimated effort to review (1-5, lower is better): 2

[jserv]

Benchmarks

Benchmark suite	Current: d470cd5	Previous: 2889609	Ratio
Dhrystone	1316 Average DMIPS over 10 runs	1300 Average DMIPS over 10 runs	0.99
Coremark	918.562 Average iterations/sec over 10 runs	929.824 Average iterations/sec over 10 runs	1.01

This comment was automatically generated by workflow using github-action-benchmark.

[jserv]

Don't touch src/softfloat.

[visitorckw]

How about rewriting it this way to avoid repeating the same logic twice?

diff --git a/src/decode.c b/src/decode.c
index f65556d..a8ba70e 100644
--- a/src/decode.c
+++ b/src/decode.c
@@ -1983,6 +1983,8 @@ typedef bool (*decode_t)(rv_insn_t *ir, uint32_t insn);
 /* decode RISC-V instruction */
 bool rv_decode(rv_insn_t *ir, uint32_t insn)
 {
+    bool ret;
+
     assert(ir);
 
 #define OP_UNIMP op_unimp
@@ -2026,7 +2028,8 @@ bool rv_decode(rv_insn_t *ir, uint32_t insn)
         /* decode instruction (compressed instructions) */
         const decode_t op = rvc_jump_table[c_index];
         assert(op);
-        return op(ir, insn);
+        ret = op(ir, insn);
+        goto final;
     }
 #endif
 
@@ -2036,8 +2039,17 @@ bool rv_decode(rv_insn_t *ir, uint32_t insn)
     /* decode instruction */
     const decode_t op = rv_jump_table[index];
     assert(op);
-    return op(ir, insn);
+    ret = op(ir, insn);
 
 #undef OP_UNIMP
 #undef OP
+
+final:
+
+#if RV32_HAS(RV32E)
+    if (unlikely(ir->rd > 15 || ir->rs1 > 15 || ir->rs2 > 15 || ir->rs3 > 15))
+        return false;
+#endif
+
+    return ret;
 }

[ChinYikMing]

The system emulation CI can be rerun and should be fixed.

Related: #579

[ChinYikMing]

The system emulation CI can be rerun and should be fixed.

Related: #579

@jserv Please merge #579 first, then rebase and the CI for this PR will be passed.

[jserv]

Rebase the latest master branch as @ChinYikMing requested.

[jserv]

Can you check the failure of RISC-V Architectural Tests reported by CI?

[jserv]

Thank @eleanorLYJ for contributing!