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[Kernel] support merge_attn_states CUDA kernel, 3x speedup #16173
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Signed-off-by: DefTruth <[email protected]>
Signed-off-by: DefTruth <[email protected]>
👋 Hi! Thank you for contributing to the vLLM project. 💬 Join our developer Slack at https://slack.vllm.ai to discuss your PR in #pr-reviews, coordinate on features in #feat- channels, or join special interest groups in #sig- channels. Just a reminder: PRs would not trigger full CI run by default. Instead, it would only run Once the PR is approved and ready to go, your PR reviewer(s) can run CI to test the changes comprehensively before merging. To run CI, PR reviewers can either: Add 🚀 |
Signed-off-by: DefTruth <[email protected]>
Signed-off-by: DefTruth <[email protected]>
Signed-off-by: DefTruth <[email protected]>
Signed-off-by: DefTruth <[email protected]>
Signed-off-by: DefTruth <[email protected]>
Signed-off-by: DefTruth <[email protected]>
Signed-off-by: DefTruth <[email protected]>
Signed-off-by: DefTruth <[email protected]>
@WoosukKwon, @tlrmchlsmth Hi~ This PR is ready. Could you please take a look? Compared to the Triton kernel, the CUDA kernel implemented in this PR can achieve a maximum speedup of over |
@WoosukKwon, @tlrmchlsmth End2End performance improved for R1 with PP=3 + TP=8 on L20, 4K IN:1K OUT (TTFT 5687.80 ms -> 5654.02 ms), 16 concurrency. |
This pull request has merge conflicts that must be resolved before it can be |
Signed-off-by: DefTruth <[email protected]>
Signed-off-by: DefTruth <[email protected]>
Signed-off-by: DefTruth <[email protected]>
Signed-off-by: DefTruth <[email protected]>
Signed-off-by: DefTruth <[email protected]>
Signed-off-by: DefTruth <[email protected]>
Signed-off-by: DefTruth <[email protected]>
Signed-off-by: DefTruth <[email protected]>
Signed-off-by: DefTruth <[email protected]>
Lint and Deploy CI failed, but seems not related to this PR. ERROR 04-10 04:06:36 [registry.py:345] from torch._inductor.runtime.hints import DeviceProperties
ERROR 04-10 04:06:36 [registry.py:345] File "/opt/venv/lib/python3.12/site-packages/torch/_inductor/runtime/hints.py", line 67, in <module>
ERROR 04-10 04:06:36 [registry.py:345] from triton.compiler.compiler import AttrsDescriptor
ERROR 04-10 04:06:36 [registry.py:345] ImportError: cannot import name 'AttrsDescriptor' from 'triton.compiler.compiler' (/opt/venv/lib/python3.12/site-packages/triton/compiler/compiler.py) |
@WoosukKwon , @tlrmchlsmth @mgoin Hi~ This PR is ready. Could you please take a look? |
Signed-off-by: DefTruth <[email protected]>
Signed-off-by: DefTruth <[email protected]>
Signed-off-by: DefTruth <[email protected]>
Signed-off-by: DefTruth <[email protected]>
Signed-off-by: DefTruth <[email protected]>
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Thank you very much for the careful work and verbose testing, we appreciate it! I think this is essentially good to go given the results you've already shared. Just a few questions
Signed-off-by: DefTruth <[email protected]>
Signed-off-by: DefTruth <[email protected]>
@mgoin AMD build failed, should I add the #ifndef USE_ROCM macro restriction when binding in PyTorch? #13 96.26 /app/vllm/csrc/torch_bindings.cpp:78:48: error: ‘merge_attn_states’ was not declared in this scope
--
| #13 96.26 78 \| ops.impl("merge_attn_states", torch::kCUDA, &merge_attn_states);
| #13 96.26 \| ^~~~~~~~~~~~~~~~~
like this #ifndef USE_ROCM
// Merge attn states
// Implements section 2.2 of https://www.arxiv.org/pdf/2501.01005
// can be used to combine partial attention results (in the split-KV case)
ops.def(
"merge_attn_states("
" Tensor! output,"
" Tensor!? output_lse,"
" Tensor prefix_output,"
" Tensor prefix_lse,"
" Tensor suffix_output,"
" Tensor suffix_lse) -> ()");
ops.impl("merge_attn_states", torch::kCUDA, &merge_attn_states);
#endif |
Signed-off-by: DefTruth <[email protected]>
Head branch was pushed to by a user without write access
@mgoin All tests passed~ PTAL. |
base on vllm/attention/ops/triton_merge_attn_states.py
Use CUDA kernel instead of Triton to minimize CPU overhead. Compared to the Triton kernel, the CUDA kernel implemented in this PR can achieve a maximum speedup of over
3x
. @WoosukKwon, End2End performance improved for R1 with PP=3 + TP=8 on L20, 4K IN:1K OUT (TTFT 5687.80 ms -> 5654.02 ms). The performance of inference will not degrade.Performance
cases for MLA with TP=8, num query heads per rank is 16, headsize is 128.
Correctness
show more details
- float32 (performance & correctness)End2End test
R1 671B with L20x3, PP=3, TP=8
4K IN:1K OUT (TTFT 5687.80 ms -> 5654.02 ms), The performance of inference will not degrade.
show more details
4K IN:1K OUT (TTFT 5687.80 ms -> 5654.02 ms)
8K IN:64 OUT (TTFT 8861.07ms -> 8767.16ms)
CEval benchmark (0.90197884615385)
We use evalscope to run benchmark on
CEval
dataset.Total AverageAccuracy: 0.90197884615385
show more details
Test cascade_flash_attn