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Stage2 riscv64 support #5984
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Stage2 riscv64 support #5984
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@FireFox317 I didn't expect them to be working properly, but they seem to be working and are the correct size. This outputs correctly on at least x86_64 and i386 and mipsel and aarch64: pub fn main() !void {
const Stru = packed struct {
opcode: u7,
rd: u5,
unused: u3 = 0,
rsi1: u5,
imm11: u11,
signextend: u1 = 0,
};
@import("std").debug.warn("{b:0>32}\n", .{@intCast(u32, 0b01100000000100001000000010000001)});
@import("std").debug.warn("{b:0>32}\n", .{@bitCast(u32, Stru{ .imm11 = 0b11000000001, .rsi1 = 1, .rd = 1, .opcode = 1 })});
} |
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This all looks good. Should be pretty simple to slap a compare_output test case on there and then I think it's merge ready.
src-self-hosted/codegen.zig
Outdated
switch (reg.size()) { | ||
64 => return self.genSetReg(src, reg, .{ .immediate = 0xaaaaaaaaaaaaaaaa }), | ||
else => unreachable, | ||
} |
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No need for this switch right? If all registers are always 64 bits.
The size and to64 functions should probably be removed too. Those are
only needed for x64, they don't represent a concrete interface.
…-- Email domain proudly hosted at https://migadu.com
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I'll make a change in master branch regarding the to64 things that should clear up how to (not have to) do it for other architectures |
Nice work! Merged in e4eb439. In that branch before merging I also made ...actually I forgot to check that the test was working, looks like it's not failing when I mangle the "hello world" text. Will push a follow-up commit shortly. But anyway the code is merged into master. |
Fixed in d61a9e3:
|
(
{x0}
…{x31}
also work as register names)Still need to do:
ra
in functionsnotes for anyone else making a backend