The code

.github/workflows/ci.yml

@@ -0,0 +1,50 @@
+on:
+  pull_request:
+
+name: Continuous integration
+
+# Make sure CI fails on all warnings, including Clippy lints
+env:
+  RUSTFLAGS: "-Dwarnings"
+
+jobs:
+  ci:
+    runs-on: ubuntu-latest
+    strategy:
+      matrix:
+        rust:
+          - stable
+        device:
+          - stm32f334x4
+          - stm32f334x6
+          - stm32f334x8
+
+          - stm32h742
+          - stm32h743
+          #- stm32h745
+          - stm32h747cm7
+          - stm32h750
+          - stm32h753
+          #- stm32h755
+          #- stm32h757
+
+          - stm32g474
+          - stm32g484
+        features:
+          - defmt
+
+    steps:
+      - uses: actions/checkout@v2
+      - uses: actions-rs/toolchain@v1
+        with:
+          profile: minimal
+          toolchain: ${{ matrix.rust }}
+          target: thumbv7em-none-eabihf
+          override: true
+
+      - name: Regular build
+        run: cargo check --features ${{ matrix.device }} --features ${{ matrix.features }}
+      - name: Build examples
+        run: cargo check --examples --features ${{ matrix.device }} --features ${{ matrix.features }}
+      - name: Clippy
+        run: cargo clippy --examples --features ${{ matrix.device }} --features ${{ matrix.features }}

Cargo.toml

@@ -4,13 +4,28 @@ version = "0.1.0"
 edition = "2021"
 
 [dependencies]
-stm32f3 = { version = "0.15.1", optional = true }
-stm32h7 = { version = "0.15.1", optional = true }
-stm32g4 = { version = "0.19.0", package = "stm32g4-staging", optional = true }
 
-stm32f3xx-hal = { version = "0.10.0", optional = true }
-stm32h7xx-hal = { version = "0.16.0", optional = true }
-stm32g4xx-hal = { version = "0.0.1", optional = true }
+stm32f3 = { git = "https://github.com/stm32-rs/stm32-rs-nightlies", optional = true }
+stm32h7 = { git = "https://github.com/stm32-rs/stm32-rs-nightlies", fatures = ["critical-section"], optional = true }
+#stm32g4 = { git = "", optional = true }
+
+#stm32f3xx-hal = { version = "0.10.0", optional = true }
+stm32f3xx-hal = { git = "https://github.com/usbalbin/stm32f3xx-hal", branch = "update_for_new_pac", optional = true }
+#stm32h7xx-hal = { version = "0.16.0", optional = true }
+stm32h7xx-hal = { git = "https://github.com/usbalbin/stm32h7xx-hal", branch = "update_for_new_pac", optional = true }
+#stm32h7xx-hal = { path = "../stm32h7xx-hal", optional = true }
+
+#stm32g4xx-hal = { version = "0.0.1", optional = true }
+stm32g4xx-hal = { git = "https://github.com/stm32-rs/stm32g4xx-hal", branch = "staged-pac", optional = true }
+#stm32g4xx-hal = { path = "../stm32g4xx-hal", optional = true }
+defmt = { version = "0.3.10", optional = true }
+fugit = "0.3.7"
+
+[dev-dependencies]
+cortex-m = { version = "0.7.7", features = ["critical-section-single-core"] }
+defmt-rtt = "0.4.0"
+cortex-m-rt = "0.7.2"
+panic-probe = { version = "0.3.0", features = ["print-defmt"] }
 
 [features]
 default = []
@@ -19,18 +34,85 @@ hrtim_v1 = []
 hrtim_v1_1 = []
 hrtim_v2 = []
 
+stm32f3 = ["stm32f3/stm32f3x4"]
+stm32h7 = ["dep:stm32h7"]
+stm32g4 = []
+
 stm32f334x4 = ["stm32f3", "stm32f3xx-hal/stm32f334x4", "hrtim_v1"]
 stm32f334x6 = ["stm32f3", "stm32f3xx-hal/stm32f334x6", "hrtim_v1"]
 stm32f334x8 = ["stm32f3", "stm32f3xx-hal/stm32f334x8", "hrtim_v1"]
 
 stm32h742 = ["stm32h7", "stm32h7xx-hal/stm32h742", "hrtim_v1_1"]
 stm32h743 = ["stm32h7", "stm32h7xx-hal/stm32h743", "hrtim_v1_1"]
 #stm32h745 = ["stm32h7", "stm32h7xx-hal/stm32h745", "hrtim_v1_1"]
-#stm32h747 = ["stm32h7", "stm32h7xx-hal/stm32h747", "hrtim_v1_1"]
+stm32h747cm7 = ["stm32h7", "stm32h7xx-hal/stm32h747cm7", "hrtim_v1_1"]
 stm32h750 = ["stm32h7", "stm32h7xx-hal/stm32h750", "hrtim_v1_1"]
 stm32h753 = ["stm32h7", "stm32h7xx-hal/stm32h753", "hrtim_v1_1"]
 #stm32h755 = ["stm32h7", "stm32h7xx-hal/stm32h755", "hrtim_v1_1"]
 #stm32h757 = ["stm32h7", "stm32h7xx-hal/stm32h757", "hrtim_v1_1"]
 
 stm32g474 = ["stm32g4", "stm32g4xx-hal/stm32g474", "hrtim_v2"]
-stm32g484 = ["stm32g4", "stm32g4xx-hal/stm32g484", "hrtim_v2"]
+stm32g484 = ["stm32g4", "stm32g4xx-hal/stm32g484", "hrtim_v2"]
+defmt = ["dep:defmt", "fugit/defmt"]
+
+# F3
+
+[[example]]
+name = "stm32f3"
+required-features = ["stm32f3"]
+path = "examples/stm32f3/hrtim.rs"
+
+
+# G4
+
+[[example]]
+name = "stm32g4-adc-trigger"
+required-features = ["stm32g4"]
+path = "examples/stm32g4/adc-trigger.rs"
+
+[[example]]
+name = "stm32g4-capture"
+required-features = ["stm32g4"]
+path = "examples/stm32g4/capture.rs"
+
+[[example]]
+name = "stm32g4-capture-dma"
+required-features = ["stm32g4"]
+path = "examples/stm32g4/capture-dma.rs"
+
+[[example]]
+name = "stm32g4-eev-comp"
+required-features = ["stm32g4"]
+path = "examples/stm32g4/eev-comp.rs"
+
+[[example]]
+name = "stm32g4-eev"
+required-features = ["stm32g4"]
+path = "examples/stm32g4/eev.rs"
+
+[[example]]
+name = "stm32g4-flt-comp"
+required-features = ["stm32g4"]
+path = "examples/stm32g4/flt-comp.rs"
+
+[[example]]
+name = "stm32g4-flt"
+required-features = ["stm32g4"]
+path = "examples/stm32g4/flt.rs"
+
+[[example]]
+name = "stm32g4"
+required-features = ["stm32g4"]
+path = "examples/stm32g4/hrtim.rs"
+
+[[example]]
+name = "stm32g4-master"
+required-features = ["stm32g4"]
+path = "examples/stm32g4/master.rs"
+
+# H7
+
+[[example]]
+name = "stm32h7"
+required-features = ["stm32h7"]
+path = "examples/stm32h7/hrtim.rs"

examples/stm32f3/hrtim.rs

@@ -0,0 +1,107 @@
+#![no_std]
+#![no_main]
+
+use cortex_m_rt::entry;
+use panic_probe as _;
+use stm32_hrtim::{
+    compare_register::HrCompareRegister, control::HrControltExt, output::HrOutput, timer::HrTimer,
+    HrParts, HrPwmAdvExt, Pscl4,
+};
+use stm32f3xx_hal::{
+    delay::Delay,
+    flash::FlashExt as _,
+    gpio::GpioExt,
+    pac::{CorePeripherals, Peripherals},
+    prelude::{_embedded_hal_blocking_delay_DelayMs, _stm32f3xx_hal_time_rate_Extensions},
+    rcc::RccExt,
+};
+
+#[entry]
+fn main() -> ! {
+    defmt::info!("Initializing...");
+
+    let dp = Peripherals::take().expect("cannot take peripherals");
+    let cp = CorePeripherals::take().expect("cannot take core");
+
+    let mut flash = dp.FLASH.constrain();
+    let mut rcc = dp.RCC.constrain();
+    let mut gpioa = dp.GPIOA.split(&mut rcc.ahb);
+
+    // Set system frequency to 64MHz using PLL, PLLCLKx2 will thus be 128MHz which
+    // feeds into the HRTIM. This and the HRTIM's DLL would lead to an effective
+    // HRTIM frequency of 128MHz * 32 = 4.096GHz...
+    let clocks = rcc
+        .cfgr
+        .sysclk(64_u32.MHz())
+        .use_pll()
+        .freeze(&mut flash.acr);
+
+    let mut delay = Delay::new(cp.SYST, clocks);
+
+    // ...with a prescaler of 4 this gives us a HrTimer with a tick rate of 1024MHz
+    // With max the max period set, this would be 1024MHz/2^16 ~= 15.6kHz...
+    let prescaler = Pscl4;
+
+    let pin_a = gpioa.pa8;
+    let pin_b = gpioa.pa9;
+
+    //        .               .               .               .
+    //        .  30%          .               .               .
+    //         ----           .               .----           .
+    //out1    |    |          .               |    |          .
+    //        |    |          .               |    |          .
+    // --------    ----------------------------    --------------------
+    //        .               .----           .               .----
+    //out2    .               |    |          .               |    |
+    //        .               |    |          .               |    |
+    // ------------------------    ----------------------------    ----
+    //        .               .               .               .
+    //        .               .               .               .
+    let (hr_control, ..) = dp
+        .HRTIM_COMMON
+        .hr_control(&clocks, &mut rcc.apb2)
+        .wait_for_calibration();
+    let mut hr_control = hr_control.constrain();
+
+    let HrParts {
+        mut timer,
+        mut cr1,
+        out: (mut out1, mut out2),
+        ..
+    } = dp
+        .HRTIM_TIMA
+        .pwm_advanced((pin_a, pin_b))
+        .prescaler(prescaler)
+        .period(0xFFFF)
+        .push_pull_mode(true) // Set push pull mode, out1 and out2 are
+        // alternated every period with one being
+        // inactive and the other getting to output its wave form
+        // as normal
+        .finalize(
+            &mut hr_control,
+            &mut gpioa.moder,
+            &mut gpioa.otyper,
+            &mut gpioa.afrh,
+        );
+
+    out1.enable_rst_event(&cr1); // Set low on compare match with cr1
+    out2.enable_rst_event(&cr1);
+
+    out1.enable_set_event(&timer); // Set high at new period
+    out2.enable_set_event(&timer);
+
+    out1.enable();
+    out2.enable();
+
+    loop {
+        // Step frequency from 15.6kHz to about 156kHz(half of that when only looking at one pin)
+        for i in 1..=10 {
+            let new_period = u16::MAX / i;
+
+            cr1.set_duty(new_period / 3);
+            timer.set_period(new_period);
+
+            delay.delay_ms(500_u16);
+        }
+    }
+}